1. Field of the Invention
The present invention relates to a data reception system for receiving data from a predetermined transmission path.
2. Description of the Related Art
Systems for transmitting and receiving information through a transmission path of a network, such as a LAN (Local Area Network), are spreading. Ethernet (registered trademark) is one of standards of such systems.
According to the Ethernet, data transmission and reception processes are performed by a controller (a CPU: Central Processing Unit) of a system as a whole and an access control unit (MAC: Media Access Controller) using transmission and reception descriptors. A descriptor is transmission/reception control information indicating the direction of a data transfer (transmission or reception), the storage position (address) of the transmitted or received data in a storage area, and the size of the data. In particular, a reception descriptor is a record of an address of a buffer memory where received data is stored.
For example, when data are transmitted, the CPU generates a transmission descriptor, and the MAC reads the data to be transmitted from the buffer memory by referring to the transmission descriptor and transmits the data. On the contrary, when data are received, the CPU generates a reception descriptor, and the MAC writes the received data in the buffer memory and updates the reception descriptor based on the address of the written data.
A description now will be given of an example of an apparatus for receiving data through a transmission path, such as the Ethernet, according to the related art.
FIG. 1 is a block diagram showing an example of a configuration of a data reception system 200 according to the related art.
As shown in FIG. 1, the data reception system 200 includes a data acquisition unit 201, a MAC 202, a temporary storage area 203, a data storage area 204, a descriptor area 205, and a CPU 206.
The data acquisition unit 201 is physically connected to a transmission path through a LAN cable to acquire data from the transmission path. Data equal to or smaller than a predetermined data size are continually transmitted from the transmission path, and the data acquisition unit 201 therefore continually receives data. The data acquisition unit 201 is directly connected to the MAC 202, which will be described later, and the unit transfers data acquired from the transmission path to the MAC 202.
The MAC 202 controls the reception of data by referring to a reception descriptor generated by the CPU 206, which will be described later. First, the MAC 202 temporarily stores the data acquired by the data acquisition unit 201 in the temporary storage area 203, which will be described later. Thereafter, the MAC refers to the reception descriptor that is stored in the descriptor area to transfer the data to a position in the data storage area 204 described in the reception descriptor on a DMA (Direct Memory Access) basis, thereby storing the data in that position. Details of the reception process exercised by the MAC 202 will be described later.
The MAC 202 includes the temporary storage area 203.
The temporary storage area 203 is a storage area for temporarily storing data received by the MAC 202 before storing the data in the data storage area 204, which will be descried later. The temporary storage area 203 is provided for the purpose of absorbing a delay that occurs when the data received by the MAC 202 is transferred to the data storage area 204 and stored therein.
The data storage area 204 is a storage area for storing received data. The CPU 206, which will be described later, executes predetermined processes using data stored in the data storage area 204.
The descriptor area 205 is a storage area for storing descriptors generated by the CPU 206, and a predetermined number of descriptors can be stored in the area.
The CPU 206 is an arithmetic control unit for controlling the data reception system 200 as a whole.
The CPU 206 reads data stored in the data storage area 204 and executes predetermined processes using the data.
Further, the CPU 206 generates transmission and reception descriptors in preparation for the transmission and reception of information and stores them in the descriptor area 205.
An example of a data receiving operation of such a data reception system 200 according to the related art is as follows.
The CPU 206 generates a plurality of descriptors (reception descriptors) in preparation for the reception of a plurality of pieces of data, stores the descriptors in the descriptor area 205, and notifies the MAC 202 of the presence of the descriptors thus generated. The MAC 202 stores data acquired by the data acquisition unit 201 from the transmission path in the temporary storage area 203 as received data. When the MAC 202 is notified of the presence of the new descriptors by the CPU 206, the MAC transfers the received data stored in the temporary storage area 203 on a DMA basis to store the data in the data storage area 204 based on the information described in relevant descriptors. When the transfer is finished, the MAC 202 updates the descriptors that have been referred to based on the amount of the received data that has been transferred and information on the storage position of the data (information on the address of the data in the data storage area), and the MAC notifies the CPU 206 of the completion of reception. The CPU 206 reads the data that has been received from the data storage area 204 and executes a predetermined process using the data thus read. Such a process is repeated for each set of data having a predetermined size acquired by the data acquisition unit 201.
An example of such a data transmission/reception apparatus according to the related art is disclosed in JP-A-05-158865 (Patent Document 1).